1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a silicon-oxide-nitride-oxide-silicon (SONOS) memory device having an enhanced integration density without increasing an area of the semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
Data storage capacity of a semiconductor memory device is proportional to the number of memory cells per unit area, or integration density, of the device.
Typically, each memory cell consists of one transistor and one capacitor. Therefore, it is possible to enhance the integration density of a semiconductor memory device by scaling-down a size of the transistor and the capacitor. Since early semiconductor memory devices of low integration density have sufficient margins for a photo-etching process, scaling-down of transistors and capacitors has had a positive effect to some degree.
The integration density of a semiconductor memory device is closely related to a design rule applied in a semiconductor manufacturing process. In order to enhance the integration density of the semiconductor memory device, the design rule should be strictly respected. The strictly respected design rule implies a reduction of the margins for a photo-etching process and demands precision in the photo-etching process.
In most cases, reduction of the margins in the photo-etching process results in the degradation of yield in the semiconductor manufacturing process. Therefore, it is necessary to develop a new method for enhancing integration density of a semiconductor memory device while preventing degradation in the yield thereof.
In an effort to enhance integration density of a semiconductor memory device, novel semiconductor memory devices have been introduced, which are differently configured from a conventional memory cell and have a data storage medium different from a conventional capacitor, e.g., giant magnetoresistance (GMR) or tunneling magnetoresistance (TMR), on a transistor.
A silicon-oxide-nitride-oxide-silicon (SONOS) memory device is one type of the newly introduced semiconductor memory devices. FIG. 1 illustrates a cross-section of a conventional SONOS memory device.
Referring to FIG. 1, the conventional SONOS memory device includes a p-type semiconductor substrate 10 and a gate stack 11 placed on a predetermined region of the p-type semiconductor substrate 10. A source region 12 and a drain region 14 are formed in the p-type semiconductor substrate 10 at sides of the gate stack 11, to which an n-type conductive impurity is implanted. The source region 12 and the drain region 14 are extended under portions of the gate stack 11. A channel region 16 is formed between the source region 12 and the drain region 14 under the gate stack 11. The gate stack 11 includes a memory node 24 formed on a predetermined region including the channel region 16 of the p-type semiconductor substrate 10, and a gate conductive layer 26, i.e., a control gate, formed on the memory node 24. The memory node 24 includes a tunneling oxide layer 18 formed on the predetermined region including the channel region 16 of the p-type semiconductor substrate 10, a nitride layer 20 formed on the tunneling oxide layer 18, and a blocking oxide layer 22 formed on the nitride layer 20. The nitride layer 20 is used to trap electrons tunneling into the tunneling oxide layer 18 and has trap sites therein. Reference numeral 28 indicates electrons trapped in the nitride layer 20. The blocking oxide layer 22 is used to prevent the electrons trapped in the nitride layer 20 from moving to the gate conductive layer 26.
Since the conventional SONOS memory device has only one threshold voltage, only one data value can be stored therein. Thus, in order to store more data, more SONOS memory devices are needed in proportion to the number of data. Therefore, in order to store more data, the integration density of the semiconductor memory device should be increased. To increase the integration density of the semiconductor memory device, it is necessary to reduce the size of the memory device shown in FIG. 1. Thus, the strictly respected design rule should be applied in the photo-etching process. However, this is a difficult task because of limitations of an exposure process, such as a limitation of resolution.
As such, although the integration density of the conventional SONOS memory device may be enhanced as compared with the conventional memory cell, the extent of such enhancement is limited due to limitations of the exposure process.